View CY7C09099V-7AXI_9096162.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

cy7c09099v cy7c09179v 3.3 v 32k/128k 8/9 synchronous dual-port static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-06043 rev. *h revised june 17, 2014 3.3 v 32 k/64 k/128 k 8/9 synchronous dual-port static ram features true dual-ported memory cells which enable simultaneous access of the same memory location flow-through and pipelined devices 32k 9 organizations (cy7c09179v) 128k 8 organizations (cy7c09099v) three modes ? flow-through ? pipelined ? burst pipelined output mode on both ports enables fast 100-mhz operation 0.35-micron cmos for optimum speed and power high-speed clock to data access 7.5 [1] /12 ns (max.) 3.3-v low operating power ? active = 115 ma (typical) ? standby = 10 ? a (typical) fully synchronous interface for easier operation burst counters increment addresses internally shorten cycle times minimize bus noise supported in flow-through and pipelined modes dual chip enables for easy depth expansion automatic power down commercial and industrial temperature ranges available in 100-pin tqfp pb-free packages available note 1. see page 9 and page 10 for load conditions. cy7c09079v/89v/99v cy7c09179v/89v/99v
cy7c09099v cy7c09179v document number: 38-06043 rev. *h page 2 of 28 logic block diagram r/w l ce 0l ce 1l oe l ft /pipe l i/o 0l ?i/o 7/8l control a 0 ?a 14/15/16l clk l ads l cnten l cntrst l r/w r 1 0 0/1 ce 0r ce 1r oe r 1 0/1 0 ft /pipe r i/o 0r ?i/o 7/8r i/o control a 0 ?a 14/15/16r clk r ads r cnten r cntrst r 1 0 0/1 1 0/1 0 i/o counter/ address register decode true dual-ported ram array counter/ address register decode 8/9 8/9 [2] [2] [3] [3] 15/16/17 15/16/17 notes 2. i/o 0 ?i/o 7 for 8 devices, i/o 0 ?i/o 8 for 9 devices 3. a 0 ?a 14 for 32k and a 0 ?a 16 for 128k devices
cy7c09099v cy7c09179v document number: 38-06043 rev. *h page 3 of 28 functional description the cy7c09099v and cy7c09179v are high speed synchronous cmos 128k 8 and 32k 9 dual-port static rams. two ports are provided, permitting independent, simulta- neous access for reads and writes to any location in memory. [4] registers on control, address, and data lines enable minimal setup and hold times. in pipelined output mode, data is regis- tered for decreased cycle ti me. clock to data valid t cd2 =7.5 ns [5] (pipelined). flow-through mode can also be used to bypass the pipelined output register to eliminate access latency. in flow-through mode, data is available t cd1 = 22 ns after the address is clocked into the device. pipelined output or flow-through mode is selected via the ft /pipe pin. each port contains a burst count er on the input address register. the internal write pulse width is independent of the low-to-high transition of the clock signal. the internal write pulse is self-timed to enable th e shortest possible cycle times. a high on ce 0 or low on ce 1 for one clock cycle powers down the internal circuitry to reduce the static power consumption. the use of multiple chip enables enables easier banking of multiple chips for depth expansion configurations. in the pipelined mode, one cycle is required with ce 0 low and ce 1 high to reactivate the outputs. counter enable inputs are provided to stall the operation of the address input and use the internal address generated by the internal counter for fast interleaved memory applications. a port?s burst counter is loaded with the port?s address strobe (ads ). when the port?s count enable (cnten ) is asserted, the address counter increments on each low-to-high transition of that port?s clock signal. this reads/writes one word from/into each successive address location until cnten is deasserted. the counter can address the entire memory array and loops back to the start. counter reset (cntrst ) is used to reset the burst counter. all parts are available in 100-pin thin quad plastic flatpack (tqfp) packages. notes 4. when writing simultaneously to the same location, the final value cannot be guaranteed. 5. see page 9 and page 10 for load conditions.
cy7c09099v cy7c09179v document number: 38-06043 rev. *h page 4 of 28 contents pin configurations ........................................................... 5 selection guide ................................................................ 7 pin definitions .................................................................. 7 maximum ratings ............................................................. 8 operating range ............................................................... 8 electrical characteristics ................................................. 8 capacitance ...................................................................... 9 switching characteristics .............................................. 11 switching waveforms .................................................... 12 read/write and enable operation.................................. 23 address counter control operation............................. 23 ordering information ...................................................... 24 128 k 8 3.3 v synchronous dual-port sram ........ 24 32 k 9 3.3 v synchronous dual-port sram.......... 24 ordering code definitions ..... .................................... 24 package diagram ............................................................ 25 acronyms ........................................................................ 26 document conventions ................................................. 26 units of measure ....................................................... 26 document history page ................................................. 27 sales, solutions, and legal information ...................... 28 worldwide sales and design s upport ......... .............. 28 products .................................................................... 28 psoc solutions ......................................................... 28
cy7c09099v cy7c09179v document number: 38-06043 rev. *h page 5 of 28 pin configurations figure 1. 100-pin tqfp (top view) - cy7c09099v (128k 8) 1 3 2 92 91 90 84 85 87 86 88 89 83 82 81 76 78 77 79 80 93 94 95 96 97 98 99 100 59 60 61 67 66 64 65 63 62 68 69 70 75 73 74 72 71 nc nc a7r a8r a9r a10r a15r a12r a14r gnd nc nc ce 0r a13r a11r nc nc ce1r cntrst r r/wr oe r ft /piper gnd nc a16r 58 57 56 55 54 53 52 51 nc nc a7l a8l a9l a10l a15l a12l a14l vcc nc nc ce 0l a13l a11l nc nc ce1l cntrst l r/w l oe l ft /pipel nc nc a16l 17 16 15 9 10 12 11 13 14 8 7 6 4 5 18 19 20 21 22 23 24 25 nc nc a6l a5l a4l a3l clkl a1l cntenl gnd adsr a0r a1r a0l a2l clkr cntenr a2r a3r a4r a5r a6r nc nc adsl 34 35 36 42 41 39 40 38 37 43 44 45 50 48 49 47 46 nc nc nc i/o7r i/o6r i/o5r i/01r i/o3r i/o2r gnd vcc gnd i/o2l vcc i/o4r i/o0l i/o1l i/o3l i/o4l i/o5l i/o6l i/o7l nc gnd i/o0r 33 32 31 30 29 28 27 26 cy7c09099v
cy7c09099v cy7c09179v document number: 38-06043 rev. *h page 6 of 28 figure 2. 100-pin tqfp (top view) - cy7c09179v (32k 9) 1 3 2 92 91 90 84 85 87 86 88 89 83 82 81 76 78 77 79 80 93 94 95 96 97 98 99 100 59 60 61 67 66 64 65 63 62 68 69 70 75 73 74 72 71 nc nc a7r a8r a9r a10r a15r a12r a14r gnd nc nc ce 0r a13r a11r nc nc ce1r cntrst r r/wr oe r ft /piper gnd nc a16r 58 57 56 55 54 53 52 51 nc nc a7l a8l a9l a10l a15l a12l a14l vcc nc nc ce 0l a13l a11l nc nc ce1l cntrst l r/w l oe l ft /pipel nc nc a16l 17 16 15 9 10 12 11 13 14 8 7 6 4 5 18 19 20 21 22 23 24 25 nc nc a6l a5l a4l a3l clkl a1l cntenl gnd gnd cntenr a0r a0l a2l adsr clkr a1r a2r a3r a4r a5r a6r nc adsl 34 35 36 42 41 39 40 38 37 43 44 45 50 48 49 47 46 nc nc i/o8r i/o7r i/o6r i/o5r i/01r i/o3r i/o2r gnd vcc gnd i/o2l vcc i/o4r i/o0l i/o1l i/o3l i/o4l i/o5l i/o6l i/o7l i/o8l gnd i/o0r 33 32 31 30 29 28 27 26 [6] [6] [7] [7] cy7c09179v notes 6. this pin is nc for cy7c09179v 7. this pin is nc for cy7c09179v
cy7c09099v cy7c09179v document number: 38-06043 rev. *h page 7 of 28 selection guide description cy7c09099v -7 [8] cy7c09099v cy7c09179v -12 f max2 (mhz) (pipelined) 83 50 max. access time (ns) (clock to data, pipelined) 7.5 12 typical operating current i cc (ma) 155 115 typical standby current for i sb1 (ma) (both ports ttl level) 25 20 typical standby current for i sb3 ( ? a) (both ports cmos level) 10 10 pin definitions left port right port description a 0l ?a 16l a 0r ?a 16r address inputs (a 0 ?a 14 for 32k and a 0 ?a 16 for 128k devices). ads l ads r address strobe input. used as an address qualif ier. this signal should be asserted low to access the part using an externally supplied addr ess. asserting this signal low also loads the burst counter with the address present on the address pins. ce 0l , ce 1l ce 0r , ce 1r chip enable input. to select either the left or right port, both ce 0 and ce 1 must be asserted to their active states (ce 0 ? v il and ce 1 ?? v ih ). clk l clk r clock signal. this input can be free running or strobed. maximum clock input rate is f max . cnten l cnten r counter enable input. asserting this signal lo w increments the burst address counter of its respective port on each rising edge of clk. cnten is disabled if ads or cntrst are asserted low. cntrst l cntrst r counter reset input. asserting th is signal low resets the burst address counter of its respective port to zero. cntrst is not disabled by asserting ads or cnten . i/o 0l ?i/o 8l i/o 0r ?i/o 8r data bus input/output (i/o 0 ?i/o 7 for 8 devices; i/o 0 ?i/o 8 for 9 devices). oe l oe r output enable input. this signal must be asserted low to enable the i/o data pins during read operations. r/w l r/w r read/write enable input. this signal is asserted low to write to the dual port memory array. for read operations, assert this pin high. ft /pipe l ft /pipe r flow-through/pipelined select input. for flow -through mode operation, assert this pin low. for pipelined mode operation, assert this pin high. gnd ground input. nc no connect. v cc power input. note 8. see page 9 and page 10 for load conditions.
cy7c09099v cy7c09179v document number: 38-06043 rev. *h page 8 of 28 maximum ratings exceeding maximum ratings may impair the useful life of the device. these user guidelines are not tested. [9] storage temperature ................ .............. ?65 c to +150 c ambient temperature with power applied .. .............. ........... ....... ?55 c to +125 c supply voltage to ground potential .............?0.5 v to +4.6 v dc voltage applied to outputs in high z state ...................... ?0.5 v to v cc + 0.5 v dc input voltage ................................ ?0.5 v to v cc + 0.5 v output current into outputs (low) ............................ 20 ma static discharge voltage ......................................... > 2001 v latch-up current ................................................... > 200 ma operating range range ambient temperature v cc commercial 0 c to +70 c 3.3 v ? 300 mv industrial [10] ?40 c to +85 c 3.3 v ? 300 mv electrical characteristics over the operating range parameter description cy7c09099v/ cy7c09179v unit -7 [11] -12 min typ max min typ max v oh output high voltage (v cc = min., i oh = ?4.0 ma) 2.4 ? ? 2.4 ? ? v v ol output low voltage (v cc = min., i oh = +4.0 ma) ?0.4?0.4v v ih input high voltage 2.0 ? 2.0 ? v v il input low voltage ? 0.8 ? 0.8 v i oz output leakage current ?10 10 ?10 10 ? a i cc operating current (v cc = max., i out = 0 ma) outputs disabled commercial ? 155 275 ? 115 205 ma industrial [10] 275 390 ? ? ma i sb1 standby current (both ports ttl level) [12] ce l & ce r ? v ih , f = f max commercial 25 85 20 50 ma industrial [10] 85 120 ? ? ma i sb2 standby current (one port ttl level) [12] ce l | ce r ? v ih , f = f max commercial 105 165 85 140 ma industrial [10] 165 210 ? ? ma i sb3 standby current (both ports cmos level) [12] ce l & ce r ? v cc ? 0.2 v, f = 0 commercial 10 250 10 250 ? a industrial [10] 10 250 ? ? ? a i sb4 standby current (one port cmos level) [12] ce l | ce r ? v ih , f = f max commercial 95 125 75 100 ma industrial [10] 125 170 ? ? ma notes 9. the voltage on any input or i/o pin cannot exceed the power pin during power-up. 10. industrial parts are available in cy7c09099v 11. see page 9 and page 10 for load conditions. 12. ce l and ce r are internal signals. to select either the left or right port, both ce 0 and ce 1 must be asserted to their active states (ce 0 ? v il and ce 1 ?? v ih ).
cy7c09099v cy7c09179v document number: 38-06043 rev. *h page 9 of 28 capacitance parameter description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 3.3 v 10 pf c out output capacitance 10 pf figure 3. ac test loads (a) normal load (load 1) r1 = 590 ? 3.3 v output r2 = 435 ? c= 30 pf v th = 1.4 v output c= 30 pf (b) thvenin equivalent (load 1) (c) three-state delay (load 2) r1 = 590 ? r2 = 435 ? 3.3 v output c= 5pf r th = 250 ? (used for t cklz , t olz , & t ohz including scope and jig) figure 4. ac test loads (applicable to -6 and -7 only) [13] v th = 1.4 v output c (a) load 1 (-6 and -7 only) r = 50 ? z 0 = 50 ? 3.0 v gnd 90% 90% 10% 3ns 3 ns 10% all input pulses ? ? note 13. test conditions: c = 10 pf.
cy7c09099v cy7c09179v document number: 38-06043 rev. *h page 10 of 28 figure 5. load derating curve 0.00 0.1 0 0.20 0.30 0.40 0.50 0.60 1 0 1 5 20 25 30 35 capacitance (pf) ?? (ns) for all -7 access times
cy7c09099v cy7c09179v document number: 38-06043 rev. *h page 11 of 28 switching characteristics over the operating range parameter description cy7c09099v cy7c09179v unit -7 [14] -12 min max min max f max1 f max flow-through ? 45 ? 33 mhz f max2 f max pipelined ? 83 ? 50 mhz t cyc1 clock cycle time - flow-through 22 ? 30 ? ns t cyc2 clock cycle time - pipelined 12 ? 20 ? ns t ch1 clock high time - flow-through 7.5 ? 12 ? ns t cl1 clock low time - flow-through 7.5 ? 12 ? ns t ch2 clock high time - pipelined 5 ? 8 ? ns t cl2 clock low time - pipelined 5 ? 8 ? ns t r clock rise time ? 3 ? 3 ns t f clock fall time ? 3 ? 3 ns t sa address set-up time 4 ? 4 ? ns t ha address hold time 0 ? 1 ? ns t sc chip enable set-up time 4 ? 4 ? ns t hc chip enable hold time 0 ? 1 ? ns t sw r/w set-up time 4 ? 4 ? ns t hw r/w hold time 0 ? 1 ? ns t sd input data set-up time 4 ? 4 ? ns t hd input data hold time 0 ? 1 ? ns t sad ads set-up time 4 ? 4 ? ns t had ads hold time 0 ? 1 ? ns t scn cnten set-up time 4.5 ? 5 ? ns t hcn cnten hold time 0 ? 1 ? ns t srst cntrst set-up time 4 ? 4 ? ns t hrst cntrst hold time 0 ? 1 ? ns t oe output enable to data valid ? 9 ? 12 ns t olz [15, 16] oe to low z 2 ? 2 ? ns t ohz [15, 16] oe to high z 1 7 1 7 ns t cd1 clock to data valid - flow-through ? 18 ? 25 ns t cd2 clock to data valid - pipelined ? 7.5 ? 12 ns t dc data output hold after clock high 2 ? 2 ? ns t ckhz [15, 16] clock high to output high z 2 9 2 9 ns t cklz [15, 16] clock high to output low z 2 ? 2 ? ns notes 14. see page 9 and page 10 for load conditions. 15. test conditions used are load 2. 16. this parameter is guaranteed by design, but it is not production tested.
cy7c09099v cy7c09179v document number: 38-06043 rev. *h page 12 of 28 port to port delays t cwdd write port clock high to read data delay ? 35 ? 40 ns t ccs clock to clock set-up time ? 10 ? 15 ns switching waveforms figure 6. read cycle for flow-through output (ft /pipe = v il ) [17, 18, 19, 20] switching characte ristics (continued) over the operating range parameter description cy7c09099v cy7c09179v unit -7 [14] -12 min max min max t ch1 t cl1 t cyc1 t sc t hc t dc t ohz t oe t sc t hc t sw t hw t sa t ha t cd1 t ckhz t dc t olz t cklz a n a n+1 a n+2 a n+3 q n q n+1 q n+2 clk ce 0 ce 1 r/w address data out oe notes 17. oe is asynchronously controlled; all other i nputs are synchronous to the rising clock edge. 18. ads = v il , cnten and cntrst = v ih . 19. the output is disabled (high-impedance state) by ce 0 = v ih or ce 1 = v il following the next rising edge of the clock. 20. addresses do not have to be accessed sequentially since ads = v il constantly loads the address on the rising edge of the clk. numbers are for reference only.
cy7c09099v cy7c09179v document number: 38-06043 rev. *h page 13 of 28 figure 7. read cycle for pipelined operation (ft /pipe = v ih ) [21, 22, 23, 24] switching waveforms (continued) t ch2 t cl2 t cyc2 t sc t hc t sw t hw t sa t ha a n a n+1 clk ce 0 ce 1 r/w address data out oe a n+2 a n+3 t sc t hc t ohz t oe t olz t dc t cd2 t cklz q n q n+1 q n+2 1 latency notes 21. oe is asynchronously controlled; all other i nputs are synchronous to the rising clock edge. 22. ads = v il , cnten and cntrst = v ih . 23. the output is disabled (high-impedance state) by ce 0 = v ih or ce 1 = v il following the next rising edge of the clock. 24. addresses do not have to be accessed sequentially since ads = v il constantly loads the address on the rising edge of the clk. numbers are for reference only.
cy7c09099v cy7c09179v document number: 38-06043 rev. *h page 14 of 28 figure 8. bank select pipelined read [25, 26] - switching waveforms (continued) d 3 d 1 d 0 d 2 a 0 a 1 a 2 a 3 a 4 a 5 d 4 a 0 a 1 a 2 a 3 a 4 a 5 t sa t ha t sc t hc t sa t ha t sc t hc t sc t hc t sc t hc t ckhz t dc t dc t cd2 t cklz t cd2 t cd2 t ckhz t cklz t cd2 t ckhz t cklz t cd2 t ch2 t cl2 t cyc2 clk l address (b1) ce 0(b1) data out(b2) data out(b1) address (b2) ce 0(b2) notes 25. in this depth expansion example, b1 repres ents bank #1 and b2 is bank #2; each b ank consists of one cypress dual-port device from this datasheet. address (b1) = address (b2) . 26. oe and ads = v il ; ce 1(b1) , ce 1(b2) , r/w , cnten , and cntrst = v ih .
cy7c09099v cy7c09179v document number: 38-06043 rev. *h page 15 of 28 figure 9. left port write to flow-through right port read [27, 28, 29, 30] switching waveforms (continued) t sa t ha t sw t hw t sd t hd match valid t ccs t sw t hw t dc t cwdd t cd1 match t sa t ha match no match no valid valid t dc t cd1 clk l r/w l address l data inl address r data outr clk r r/w r notes 27. the same waveforms apply for a right port write to flow-through left port read. 28. ce 0 and ads = v il ; ce 1 , cnten , and cntrst = v ih . 29. oe = v il for the right port, which is being read from. oe = v ih for the left port, which is being written to. 30. it t ccs ? maximum specified, then data from right port re ad is not valid until the maximum specified for t cwdd . if t ccs > maximum specified, then data is not valid until t ccs + t cd1 . t cwdd does not apply in this case.
cy7c09099v cy7c09179v document number: 38-06043 rev. *h page 16 of 28 figure 10. pipelined read-to-write-to-read (oe = v il ) [31, 32, 33, 34] switching waveforms (continued) t cyc2 t cl2 t ch2 t hc t sc t hw t sw t ha t sa t hw t sw t cd2 t ckhz t sd t hd t cklz t cd2 no operation write read read clk ce 0 ce 1 r/w address data in data out a n a n+1 a n+2 a n+2 d n+2 a n+3 a n+4 q n q n+3 notes 31. addresses do not have to be accessed sequentially since ads = v il constantly loads the address on the rising edge of the clk. numbers are for reference only. 32. output state (high, low, or high-impedance) is determined by the previous cycle control signals. 33. ce 0 and ads = v il ; ce 1 , cnten , and cntrst = v ih . 34. during ?no operation?, data in memory at the selected address may be corrupted and should be re-written to ensure data integ rity.
cy7c09099v cy7c09179v document number: 38-06043 rev. *h page 17 of 28 figure 11. pipelined r ead-to-write-to-read (oe controlled) [35, 36, 37, 38] switching waveforms (continued) t cyc2 t cl2 t ch2 t hc t sc t hw t sw t ha t sa a n a n+1 a n+2 a n+3 a n+4 a n+5 t hw t sw t sd t hd d n+2 t cd2 t ohz read read write d n+3 t cklz t cd2 q n q n+4 clk ce 0 ce 1 r/w address data in data out oe notes 35. addresses do not have to be accessed sequentially since ads = v il constantly loads the address on the rising edge of the clk. numbers are for reference only. 36. output state (high, low, or high-impedance) is determined by the previous cycle control signals. 37. ce 0 and ads = v il ; ce 1 , cnten , and cntrst = v ih . 38. during ?no operation?, data in memory at the selected address may be corrupted and should be re-written to ensure data integ rity.
cy7c09099v cy7c09179v document number: 38-06043 rev. *h page 18 of 28 figure 12. flow-through read-to-write-to-read (oe = v il ) [39, 40, 41, 42, 43] switching waveforms (continued) t ch1 t cl1 t cyc1 t sc t hc t sw t hw t sa t ha t sw t hw t sd t hd a n a n+1 a n+2 a n+2 a n+3 a n+4 d n+2 q n q n+1 q n+3 t cd1 t cd1 t dc t ckhz t cd1 t cd1 t cklz t dc read no operation write read clk ce 0 ce 1 address r/w data in data out notes 39. ads = v il , cnten and cntrst = v ih . 40. addresses do not have to be accessed sequentially since ads = v il constantly loads the address on the rising edge of the clk. numbers are for reference only. 41. output state (high, low, or high-impedance) is determined by the previous cycle control signals. 42. ce 0 and ads = v il ; ce 1 , cnten , and cntrst = v ih . 43. during ?no operation?, data in memory at the selected address may be corrupted and should be re-written to ensure data integ rity.
cy7c09099v cy7c09179v document number: 38-06043 rev. *h page 19 of 28 figure 13. flow-through read-to-write-to-read (oe controlled) [44, 45, 46, 47, 48] switching waveforms (continued) q n t ch1 t cl1 t cyc1 t sc t hc t sw t hw t sa t ha t cd1 t dc t ohz read a n a n+1 a n+2 a n+3 a n+4 a n+5 d n+2 d n+3 t sw t hw t sd t hd t cd1 t cd1 t cklz t dc q n+4 t oe write read clk ce 0 ce 1 address r/w data in data out oe notes 44. ads = v il , cnten and cntrst = v ih . 45. in this depth expansion example, b1 represents bank #1 and b2 is bank #2; each bank consis ts of one cypress dual-port device from this datasheet. address (b1) = address (b2) . 46. output state (high, low, or high-impedance) is determined by the previous cycle control signals. 47. ce 0 and ads = v il ; ce 1 , cnten , and cntrst = v ih . 48. during ?no operation?, data in memory at the selected address may be corrupted and should be re-written to ensure data integ rity.
cy7c09099v cy7c09179v document number: 38-06043 rev. *h page 20 of 28 figure 14. pipelined read with address counter advance [49] figure 15. flow-through read with address counter advance [49] switching waveforms (continued) counter hold read with counter t sa t ha t sad t had t scn t hcn t ch2 t cl2 t cyc2 t sad t had t scn t hcn q x-1 q x q n q n+1 q n+2 q n+3 t dc t cd2 read with counter read external address clk address ads data out cnten a n t ch1 t cl1 t cyc1 t sa t ha t sad t had t scn t hcn a n t sad t had t scn t hcn clk address ads cnten q x q n q n+1 t dc counter hold read with counter read external address read with counter q n+3 q n+2 data out t cd1 note 49. ce 0 and oe = v il ; ce 1 , r/w and cntrst = v ih .
cy7c09099v cy7c09179v document number: 38-06043 rev. *h page 21 of 28 figure 16. write with address counter advance (flow-through or pipelined outputs) [50, 51] switching waveforms (continued) t ch2 t cl2 t cyc2 a n a n+1 a n+2 a n+3 a n+4 d n+1 d n+1 d n+2 d n+3 d n+4 a n d n t sad t had t scn t hcn t sd t hd write external write with counter address write with counter write counter hold clk address internal cnten ads data in address t sa t ha notes 50. ce 0 and r/w = v il ; ce 1 and cntrst = v ih . 51. the ?internal address? is equal to the ?external address? when ads = v il and equals the counter output when ads = v ih .
cy7c09099v cy7c09179v document number: 38-06043 rev. *h page 22 of 28 figure 17. counter reset (pipelined outputs) [52, 53, 54, 55] switching waveforms (continued) t ch2 t cl2 t cyc2 clk address internal cnten ads data in address cntrst r/w data out q 0 q 1 q n d 0 a x 01a n a n+1 t sad t had t scn t hcn t srst t hrst t sd t hd t sw t hw a n a n+1 t sa t ha counter reset write address 0 read address 0 read address 1 read address n notes 52. addresses do not have to be accessed sequentially since ads = v il constantly loads the address on the rising edge of the clk. numbers are for reference only. 53. output state (high, low, or high-impedance) is determined by the previous cycle control signals. 54. ce 0 = v il ; ce 1 = v ih . 55. no dead cycle exists during counter reset. a read or write cycle may be coincidental with the counter reset.
cy7c09099v cy7c09179v document number: 38-06043 rev. *h page 23 of 28 read/write and enable operation [56, 57, 58] inputs outputs oe clk ce 0 ce 1 r/w i/o 0 ? i/o 9 operation x h x x high z deselected [59] x x l x high z deselected [59] x l h l d in write l l h h d out read [59] h x l h x high z outputs disabled address counter c ontrol operation [56, 60, 61, 62] address previous address clk ads cnten cntrst i/o mode operation x x x x l d out(0) reset counter reset to address 0 a n x l x h d out(n) load address load into counter x a n h h h d out(n) hold external address blocked?counter disabled x a n h l h d out(n+1) increment counter enabled?internal address generation notes 56. ?x? = ?don?t care?, ?h? = v ih , ?l? = v il . 57. ads , cnten , cntrst = ?don?t care.? 58. oe is an asynchronous input signal. 59. when ce changes state in the pipelined mode, deselection and read happen in the following clock cycle. 60. ce 0 and oe = v il ; ce 1 and r/w = v ih . 61. data shown for flow-through mode; pipelined mode output will be delayed by one cycle. 62. counter operation is independent of ce 0 and ce 1 .
cy7c09099v cy7c09179v document number: 38-06043 rev. *h page 24 of 28 ordering information the following table contains only the parts that are currently av ailable. if you do not see what you are looking for, contact y our local sales representative. for more inform ation, visit the cypress website at www.cypress.com and refer to the product summary page at http://www.cypre ss.com/products cypress maintains a worldwide network of offices, solution cent ers, manufacturer?s representativ es and distributors. to find th e office closest to you, visit us at http://www.cypress.com /go/datasheet/offices. ordering code definitions 128 k 8 3.3 v synchronous dual-port sram speed (ns) ordering code package name package type operating range 7.5 [63] CY7C09099V-7AXI a100 100-pin thin quad flat pack (pb-free) industrial 12 cy7c09099v-12axc a100 100-pin thin quad flat pack (pb-free) commercial 32 k 9 3.3 v synchronous dual-port sram speed (ns) ordering code package name package type operating range 12 cy7c09179v-12axc a100 100-pin thin quad flat pack (pb-free) commercial temperature range: x = c or i c = commercial; i = industrial x = pb-free (rohs compliant) package type: a = 100-pin tqfp speed grade: 12 ns or 7.5 ns v = 3.3 v x9 = depth: x = 7 or 9 7 = 32k; 9 = 128k x = width: x = 0 or 1 0 = 8; 1 = 9 09 = sync 7c = dual port sram company id: cy = cypress device 7c cy 09 v - xx x a x x x9 note 63. see page 9 and page 10 for load conditions.
cy7c09099v cy7c09179v document number: 38-06043 rev. *h page 25 of 28 package diagram figure 18. 100-pin tqfp 14 14 1.4 mm a100sa, 51-85048 51-85048 *i
cy7c09099v cy7c09179v document number: 38-06043 rev. *h page 26 of 28 acronyms document conventions units of measure acronym description cmos complementary metal oxide semiconductor i/o input/output oe output enable sram static random access memory tqfp thin quad flat pack ttl transistor-transistor logic we write enable symbol unit of measure c degree celsius mhz megahertz a microamperes ma milliamperes mm millimeter ms milliseconds mv millivolts ns nanoseconds ? ohm % percent pf picofarads vvolts wwatts
cy7c09099v cy7c09179v document number: 38-06043 rev. *h page 27 of 28 document history page document title: cy7c09099v, cy7c09179v, 3.3 v 32k/128k 8/9 synchronous dual-port static ram document number: 38-06043 rev. ecn no. orig. of change orig. of change description of change ** 110191 szv 09/29/01 change from spec number: 38-00667 to 38-06043 *a 122293 rbi 12/27/02 power up requirements added to operating conditions information *b 365034 pcn see ecn added pb-free logo added pb-free part ordering information: cy7c09089v-6axc, cy7c09089v-12axc, cy7c09099v-6axc, cy7c09099v-7ai, CY7C09099V-7AXI, cy7c09099v-12axc, cy7c09179v-6axc, cy7c09179v-12axc, cy7c09189v-6axc, cy7c09189v-12axc, cy7c09199v-6axc, cy7c09199v-7axc, cy7c09199v-9axc, cy7c09199v-9axi, cy7c09199v-12axc *c 2623658 vkn/pyrs 12/17/08 added cy7c09089v-12axi part in the ordering information table *d 2897159 rame 03/22/10 removed inactive parts from ordering information table. updated package diagram. added note in ordering information section. *e 3110406 admu 12/14/2010 updated ordering information . added ordering code definitions . *f 3264673 admu 05/24/2011 updated document title to read ?cy7c09099v, cy7c09179v, 3.3 v 32 k/64 k/128 k 8/9 synchronous dual-port static ram?. updated features . updated pin configurations (removed the note ?this pin is nc for cy7c09079v.? in page 5). updated selection guide . updated package diagram . added acronyms and units of measure . updated in new template. *g 3849285 admu 12/21/2012 updated ordering information (updated part numbers). updated package diagram : spec 51-85048 ? changed revision from *e to *g. *h 4411062 admu 06/17/2014 information for mpns cy7c09089v and cy7c09199v removed. information for -6 and -9 speed bins also removed. updated document title to ?cy7c09099v, cy7c09179v, 3.3 v 32k/128k 8/9 synchronous dual-port static ram?
document number: 38-06043 rev. *h revised june 17, 2014 page 28 of 28 all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c09099v cy7c09179v ? cypress semiconductor corporation, 2001-2014. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress.com/sales. products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5

▲Up To Search▲

Price & Availability of CY7C09099V-7AXI

	To Download CY7C09099V-7AXI Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .